KAC-9617【PDF 25/41 页】IC SENSOR IMAGE VGA 48CLCC

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IMAGE SENSOR SOLUTIONS

Functional Description (continued)

11.6 Synchronisation Signals in Slave Mode

The sensor ’s digital video port’s synchronisation signals can be

programmed to operate in slave mode. In slave mode the inte-

grated timing and control block will only start frame and row pro-

cessing upon the receipt of triggers from an external source.

Only two synchronization signals are used in slave mode as fol-

lows:

11.7 Row Trigger Input Pin (hsync)

The row trigger input pin, hsync , is used to trigger the process-

ing of a given row. It must be activated for at least two “ mclk ”

cycle. The first pixel data will appear at d[11:0] “X mclk “periods

after the assertion of the row trigger, were X mclk is given by:

X mclk = 124 + DW StAd

hsync

is the row trigger input signal.

Where:

vsync

is the frame trigger input signal.

DW StAd

is the value of the display window column start

Figure 48 shows the KAC-9617’s digital video port in slave

mode connected to a digital video processor master DVP.

address.

The polarity of the active level of the row trigger is programma-

ble. By default it is active high.

d[11:0]

hsync

vsync

pclk

mclk

KAC-9617

din[11:0]

RowTrig

FrameTrig

MasterClock

DVP

11.8 Frame Trigger Input Pin (vsync)

The frame trigger input pin, vsync , is used to reset the row

address counter and prepare the array for row processing. It

must be activated for at least one “ mclk ” cycle and no more than

96 mclk cycles after the activation of hsync as illustrated in Fig-

ure 50.

The polarity of the active level of the row trigger is programma-

ble. By default it is active high.

Figure 48. KAC-9617 in slave mode

780 clock cycles per line

hsync

pixel 11

pixel 12

pixel 652

d[11:0]

642 valid pixels

mclk

count

776 777 778 779

0

1

2

3

...

134 135 136 136 137

...

774 775 776 777 778 779

0

1

mclk

Figure 49. hsync slave mode timing diagram for centred display window of 642 pixels

780 clock cycles per line

hsync

No more than

96 clock cycles

vsync

internal row

counter

line 502

line502

line503

line 0

mclk

count

776 777 778 779

0

1

2

3

...

774 775 776 777 778 779

0

1

...

774 775 776 777 778 779

0

1

mclk

Figure 50. vsync slave mode timing diagram for scan window of 504 rows.

www.kodak.com/go/imagers 585-722-4385

25

Email:imagers@kodak.com

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相关PDF资料

KAC-9627 IC SENSOR IMAGE VGA 48CLCC

KB-A100SRW LIGHT BAR 660NM RED 8.89X3.81MM

KB-B100SRW LIGHT BAR 660NM RED 19.05X3.81MM

KB-C100SRW LIGHT BAR 660NM RED 8.89X8.89MM

KB-D100SRW LIGHT BAR 660NM RED 8.89X3.81MM

KB-E100SRW LIGHT BAR 660NM RED 8.89X3.81MM

KB-F100SRW LIGHT BAR 660NM RED 19.05X3.81MM

KB-G100SRW LIGHT BAR 660NM RED 8.89X8.89MM

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